Holtek HT45F23A Manual page 99

HT45F23A/HT45F24A
TinyPower Flash MCU with OPA & Comparators
TM
RXAK: I
Bit 0
0: Slave receive acknowledge flag
1: Slave do not receive acknowledge flag
The RXAK flag is the receiver acknowledge flag. When the RXAK flag is "0", it
means that a acknowledge signal has been received at the 9th clock, after 8 bits of data
have been transmitted. When the slave device in the transmit mode, the slave device
checks the RXAK flag to determine if the master receiver wishes to receive the next
byte. The slave transmitter will therefore continue sending out data until the RXAK
flag is "1". When this occurs, the slave transmitter will release the SDA line to allow
the master to send a STOP signal to release the I
The SIMD register is used to store the data being transmitted and received. The same register is used
by both the SPI and I
be transmitted must be placed in the SIMD register. After the data is received from the I
device can read it from the SIMD register. Any transmission or reception of data from the I
must be made via the SIMD register.
SIMD Register
Bit
Name D7
R/W R/W
POR
Bit 7~0 D7~D0: SIM Data Register bit7~bit0
SIMA Register
Bit
Name IICA6
R/W R/W
POR
IICA6~ IICA0: I
Bit 7~1
IICA6~ IICA0 is the I
The SIMA register is also used by the SPI interface but has the name SIMC2. The
SIMA register is the location where the 7-bit slave address of the slave device is
stored. Bits 7~ 1 of the SIMA register define the device slave address. Bit 0 is not
defined.
When a master device, which is connected to the I
matches the slave address in the SIMA register, the slave device will be selected. Note
that the SIMA register is the same register address as SIMC2 which is used by the SPI
interface.
Bit 0 Undefined bit
This bit can be read or written by user software program.
Rev. 1.40
C Bus Receive acknowledge flag
2
C functions. Before the device writes data to the I
2
7 6 5
D6 D5
R/W R/W
x x x
7 6 5
IICA5 IICA4
R/W R/W
x x x
C slave address
2
C slave address bit 6~ bit 0.
2
99
C Bus.
2
C bus, the actual data to
2
4 3 2
D4 D3 D2
R/W R/W R/W
x x x
4 3 2
IICA3 IICA2 IICA1
R/W R/W R/W
x x x
C bus, sends out an address, which
2
C bus, the
2
C bus
2
1 0
D1 D0
R/W R/W
x x
"x" unknown
1 0
IICA0 —
R/W —
x —
"x" unknown
March 29, 2019