A/D Operation - Holtek HT45F23A Manual

HT45F23A/HT45F24A
TinyPower Flash MCU with OPA & Comparators
TM
PCR1: Define PB4 is A/D input or not
Bit 1
0: Not A/D input
1: A/D input, AN1
PCR0: Define PB3 is A/D input or not
Bit 0
0: Not A/D input
1: A/D input, AN0

A/D Operation

The START bit in the ADCR register is used to start and reset the A/D converter. When the
microcontroller sets this bit from low to high and then low again, an analog to digital conversion
cycle will be initiated. When the START bit is brought from low to high but not low again, the
EOCB bit in the ADCR register will be set high and the analog to digital converter will be reset. It
is the START bit that is used to control the overall start operation of the internal analog to digital
converter.
The EOCB bit in the ADCR register is used to indicate when the analog to digital conversion process
is complete. This bit will be automatically set to "0" by the microcontroller after a conversion cycle
has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt
control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be
generated. This A/D internal interrupt signal will direct the program flow to the associated A/D
internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller
can be used to poll the EOCB bit in the ADCR register to check whether it has been cleared as an
alternative method of detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock f
to be either f
SYS
ADCS2~ADCS0 bits in the ACSR register.
Although the A/D clock source is determined by the system clock f
there are some limitations on the maximum A/D clock source speed that can be selected. As the
minimum value of permissible A/D clock period, t
frequencies equal to or greater than 4MHz. For example, if the system clock operates at a frequency
of 4MHz, the ADCS2~ADCS0 bits should not be set to "100". Doing so will give A/D clock periods
that are less than the minimum A/D clock period which may result in inaccurate A/D conversion
values. Refer to the following table for examples, where values marked with an asterisk * show
where, depending upon the devices, special care must be taken, as the values may be less than the
specified minimum A/D Clock Period.
ADCS2, ADCS2,
ADCS1, ADCS1,
f
SYS
ADCS0 ADCS0
= 100 = 000
(f ) (f
SYS SYS
1MHz 1µs 2µs
2MHz 500ns 1µs
4MHz 250ns* 500ns
8MHz 125ns* 250ns*
12MHz 83ns* 167ns*
Rev. 1.40
or a subdivided version of f
SYS
A/D Clock Period (t
ADCS2, ADCS2,
ADCS1, ADCS1,
ADCS0 ADCS0
= 101 = 001
/2) (f /4) (f /8)
SYS SYS
4µs 8µs
2µs 4µs
1µs 2µs
500ns 1µs
333ns* 667ns
A/D Clock Period Examples
83
. The division ratio value is determined by the
, and by bits ADCS2~ADCS0,
SYS
, is 0.5µs, care must be taken for system clock
AD
)
AD
ADCS2, ADCS2,
ADCS1, ADCS1,
ADCS0 ADCS0
= 110 = 010
(f /16) (f /32)
SYS SYS
16µs 32µs
8µs 16µs
4µs 8µs
2µs 4µs
1.33µs 2.67µs
, can be chosen
SYS
ADCS2,
ADCS1,
ADCS0
= 111
= 011
Undefined
Undefined
Undefined
Undefined
Undefined
March 29, 2019