Interrupt Priority
Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be
serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of
simultaneous requests, the following table shows the priority that is applied.
External interrupt 0
External interrupt 1
Timer/Event Counter 0 overflow
Timer/Event Counter 1 overflow
SPI/I
2
Multi-function Interrupt
The A/D converter interrupt, Time Base interrupt, External Peripheral interrupt, Comparator
interrupt, EEPROM interrupt, and LVD interrupt all share the same interrupt vector which is 18H.
Each of these interrupts has their own individual interrupt flag but also share the same MFF interrupt
flag.
The MFF flag will be cleared by hardware once the Multi-function interrupt is serviced, however the
individual interrupts that have triggered the Multi-function interrupt need to be cleared by the
application program.
INTC0 Register
Bit
7
Name
—
R/W
—
POR
—
Bit 7
unimplemented, read as "0"
T0F: Timer/Event Counter 0 interrupt request flag
Bit 6
0: inactive
1: active
EIF1: External interrupt 1 request flag
Bit 5
0: inactive
1: active
EIF0: External interrupt 0 request flag
Bit 4
0: inactive
1: active
Bit 3
ET0I: Timer/Event Counter 0 interrupt enable
0: disable
1: enable
Bit 2
EEI1: External interrupt 1 enable
0: disable
1: enable
Bit 1
EEI0: External interrupt 0 enable
0: disable
1: enable
Bit 0
EMI: Master interrupt global enable
0: disable
1: enable
Rev. 1.40
TinyPower
Flash MCU with OPA & Comparators
TM
Interrupt Source
C interrupt
6
5
T0F
EIF1
EIF0
R/W
R/W
R/W
0
0
122
HT45F23A/HT45F24A
Priority
Vector
1
04H
2
08H
3
0CH
4
10H
5
14H
6
18H
4
3
2
ET0I
EEI1
R/W
R/W
0
0
0
1
0
EEI0
EMI
R/W
R/W
0
0
March 29, 2019
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