Holtek HT45F23A Manual page 24

Instruction
TABRDC[m] PC11 PC10 PC9
TABRDL[m]
Note: PC11~PC8:Current Program Counter bits
@7~@0:Table Pointer TBLP bits
For the HT45F23A, the Table address location is 11 bits, i.e. from b10~b0
For the HT45F24A, the Table address location is 12 bits, i.e. from b11~b0
Table Program Example
The accompanying example shows how the table pointer and table data is defined and retrieved
from the HT45F24A device. This example uses raw table data located in the last page which is
stored there using the ORG statement. The value at this ORG statement is "0F00H" which refers to
the start address of the last page within the 4K Program Memory of the device. The table pointer is
setup here to have an initial value of "06H". This will ensure that the first data read from the data
table will be at the Program Memory address "0F06H" or 6 locations after the start of the last page.
Note that the value for the table pointer is referenced to the first address of the present page if the
"TABRDC [m]" instruction is being used. The high byte of the table data which in this case is equal
to zero will be transferred to the TBLH register automatically when the "TABRDL [m]" instruction
is executed.
Because the TBLH register is a read-only register and cannot be restored, care should be taken
to ensure its protection if both the main routine and Interrupt Service Routine use the table read
instructions. If using the table read instructions, the Interrupt Service Routines may change the
value of TBLH and subsequently cause errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read instructions should be avoided. However, in
situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the
execution of any main routine table-read instructions. Note that all table related instructions require
two instruction cycles to complete their operation.
Rev. 1.40
TinyPower Flash MCU with OPA & Comparators
TM
L a s t p a g e o r
T B H P R e g i s t e r
T B L P R e g i s t e r
R e g i s t e r T B L H
H i g h B y t e
Table Location Bits
b11 b10 b9 b8 b7
PC8 @7
1 1 1 1 @7
Table Location
24
HT45F23A/HT45F24A
P r o g r a m M e m o r y
D a t a
1 5 o r 1 6 b i t s
U s e r S e l e c t e d
R e g i s t e r
L o w B y t e
b6 b5 b4 b3
@6 @5 @4 @3
@6 @5 @4 @3
b2 b1 b0
@2 @1 @0
@2 @1 @0
March 29, 2019