Holtek HT45F23A Manual page 92

SIMEN: SIM Control
Bit 1
0: Disable
1: Enable
The bit is the overall on/off control for the SIM interface. When the SIMEN bit is
cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA
and SCL lines will be in a floating condition and the SIM operating current will be
reduced to a minimum value. When the bit is high the SIM interface is enabled. The
SIM configuration option must have first enabled the SIM interface for this bit to be
effective. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0
bits, the contents of the SPI control registers will remain at the previous settings when
the SIMEN bit changes from low to high and should therefore be first initialised by
the application program. If the SIM is configured to operate as an I
SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I
control bits such as HTX and TXAK will remain at the previous settings and should
therefore be first initialised by the application program while the relevant I
such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states.
Bit 0 unimplemented, read as "0"
SIMC2 Register
Bit 7
Name D7
R/W R/W
POR 0
Bit 7~6 Undefined bit
This bit can be read or written by user software program.
CKPOLB: Determines the base condition of the clock line
Bit 5
0: the SCK line will be high when the clock is inactive
1: the SCK line will be low when the clock is inactive
The CKPOLB bit determines the base condition of the clock line, if the bit is high,
then the SCK line will be low when the clock is inactive. When the CKPOLB bit is
low, then the SCK line will be high when the clock is inactive.
Bit 4 CKEG: Determines SPI SCK active clock edge type
CKPOLB=0
0: SCK is high base level and data capture at SCK rising edge
1: SCK is high base level and data capture at SCK falling edge
CKPOLB=1
0: SCK is low base level and data capture at SCK falling edge
1: SCK is low base level and data capture at SCK rising edge
The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs
and inputs data on the SPI bus. These two bits must be configured before data transfer
is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit
determines the base condition of the clock line, if the bit is high, then the SCK line
will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK
line will be high when the clock is inactive. The CKEG bit determines active clock
edge type which depends upon the condition of CKPOLB bit.
Bit 3 MLS: SPI Data shift order
0: LSB
1: MSB
This is the data shift select bit and is used to select how the data is transferred, either
MSB or LSB first. Setting the bit high will select MSB first and low for LSB first.
Rev. 1.40
TinyPower Flash MCU with OPA & Comparators
TM
6 5 4
D6 CKPOLB CKEG
R/W R/W R/W
0 0 0
92
HT45F23A/HT45F24A
C interface via the
2
3 2 1
MLS CSEN WCOL
R/W R/W R/W
0 0 0
March 29, 2019
C
2
C flags
2
0
TRF
R/W
0