Hc Frame Remaining Register (Hcfmremaining); Hc Frame Number Register (Hcfmnumber); Hc Frame Remaining Register (Hcfmremaining) Field Descriptions; Hc Frame Number Register (Hcfmnumber) Field Descriptions - Texas Instruments TMS320C6747 DSP User Manual

Processor universal serial bus (usb1.1) ohci host controller
Hide thumbs Also See for TMS320C6747 DSP:
Table of Contents

Advertisement

www.ti.com

3.15 HC Frame Remaining Register (HCFMREMAINING)

The HC frame remaining register (HCFMREMAINING) reports the number of full-speed bit times
remaining in the current frame. HCFMREMAINING is shown in
31
30
FRT
R-0
15
14
13
Reserved
R-0
LEGEND: R = Read only; -n = value after reset
Table 16. HC Frame Remaining Register (HCFMREMAINING) Field Descriptions
Bit
Field
Value
31
FRT
30-14
Reserved
13-0
FR
0-3FFFh

3.16 HC Frame Number Register (HCFMNUMBER)

The HC frame number register (HCFMNUMBER) reports the current USB frame number. HCFMNUMBER
is shown in
Figure 17
31
15
LEGEND: R = Read only; -n = value after reset
Table 17. HC Frame Number Register (HCFMNUMBER) Field Descriptions
Bit
Field
Value
31-16
Reserved
15-0
FN
0-FFFFh
SPRUFM8 – June 2009
Submit Documentation Feedback
Figure 16. HC Frame Remaining Register (HCFMREMAINING)
Description
0-1
Frame remaining toggle. This bit is loaded with the frame interval toggle bit every time the USB1.1
host controller loads the frame interval field into the frame remaining field.
0
Reserved
Frame remaining. The number of full-speed bit times remaining in the current frame. This field is
automatically reloaded with the frame interval (FI) value in the HC frame interval register
(HCFMINTERVAL) at the beginning of every frame.
and described in
Table
Figure 17. HC Frame Number Register (HCFMNUMBER)
Description
0
Reserved
Frame number. This field reports the current USB frame number. It is incremented when the frame
remaining field is reloaded with the frame interval (FI) value in the HC frame interval register
(HCFMINTERVAL). Frame number automatically rolls over from FFFFh to 0. After frame number is
incremented, its new value is written to the HCCA and the USB1.1 host controller sets the SOF
interrupt status bit and begins processing the ED lists.
Figure 16
Reserved
R-0
FR
R-0
17.
Reserved
R-0
FN
R-0
Universal Serial Bus OHCI Host Controller
Registers
and described in
Table
16.
16
0
16
0
25

Advertisement

Table of Contents
loading

Table of Contents