Hc Command And Status Register (Hccommandstatus); Hc Command And Status Register (Hccommandstatus) Field Descriptions - Texas Instruments TMS320C6747 DSP User Manual

Registers
3.3

HC Command and Status Register (HCCOMMANDSTATUS)

The HC command and status register (HCCOMMANDSTATUS) shows the current state of the host
controller and accepts commands from the host controller driver. HCCOMMANDSTATUS is shown in
Figure 4 and described in
Figure 4. HC Command and Status Register (HCCOMMANDSTATUS)
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4. HC Command and Status Register (HCCOMMANDSTATUS) Field Descriptions
Bit Field Value
31-18 Reserved 0
17-16 SOC 0-3h
15-4 Reserved 0
3 OCR 0-1
2 BLF 0-1
1 CLF 0-1
0 HCR
0
1
16 Universal Serial Bus OHCI Host Controller
Table 4.
Reserved
R-0
Reserved
R-0
Description
Reserved
Scheduling overrun count. Counts the number of times a scheduling overrun occurs. This count is
incremented even if the host controller driver has not acknowledged any previous pending scheduling
overrun interrupt.
Reserved
Ownership change request. The host controller driver sets this bit to gain ownership of the host
controller. The processor does not support SMI interrupts, so no ownership change interrupt occurs.
Bulk list filled. The host controller driver must set this bit if it modifies the bulk list to include new TDs. If
the HC current bulk register (HCBULKCURRENTED) is 0, the USB1.1 host controller does not begin
processing bulk list EDs unless this bit is set. When the USB1.1 host controller sees this bit set and
begins processing the bulk list, it clears this bit to 0.
Control list filled. The host controller driver must set this bit if it modifies the control list to include new
TDs. If the HC head control register (HCCONTROLHEADED) is 0, the USB1.1 host controller does not
begin processing control list EDs unless this bit is set. When the USB1.1 host controller sees this bit set
and begins processing the control list, it clears this bit to 0.
Host controller reset.
No effect.
Initiates a software reset of the USB1.1 host controller. This transitions the USB1.1 host controller to the
USB suspend state. This resets most USB1.1 host controller OHCI registers. OHCI register accesses
must not be attempted until a read of this bit returns a 0. A write of 1 to this bit does not reset the root
hub and does not signal USB reset to downstream USB functions.
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18 17
SOC
R-0
4 3 2 1
OCR BLF CLF
R/W-0 R/W-0 R/W-0
SPRUFM8 – June 2009
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16
0
HCR
R/W-0