Hc Operating Mode Register (Hccontrol) Field Descriptions - Texas Instruments TMS320C6747 DSP User Manual

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Table 3. HC Operating Mode Register (HCCONTROL) Field Descriptions
Bit Field Value
31-11 Reserved 0
10 RWE 0-1
9 RWC 0-1
8 IR 0
7-6 HCFS 0-3h
0
1h
2h
3h
5 BLE
0
1
4 CLE
0
1
3 IE
0
1
2 PLE
0
1
1-0 CBSR 0-3h
0
1h
2h
3h
SPRUFM8 – June 2009
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Description
Reserved
Remote wake-up enable.
Remote wake-up connected.
Interrupt routing. The USB1.1 host controller does not provide an SMI interrupt. This bit must be 0 to
allow the USB1.1 host controller interrupt to propagate to the MPU level 2 interrupt controller.
Host controller functional state. A transition to USB operational causes SOF generation to begin in 1
ms. The USB1.1 host controller can automatically transition from USB suspend to USB resume, if a
downstream resume is received. The USB1.1 host controller enters USB suspend after a software
reset. The USB1.1 host controller enters USB reset after a hardware reset. The USB reset state resets
the root hub and causes downstream signaling of USB reset.
USB reset
USB resume
USB operational
USB suspend
Bulk list enable.
The bulk ED list is not processed in the next 1 ms frame. The host controller driver can modify the bulk
ED list. If the driver removes the ED pointed to by the HC current bulk register (HCBULKCURRENTED)
from the ED list, it must update HCBULKCURRENTED to point to a current ED before it reenables the
bulk list.
Enables processing of the bulk ED list. The HC head bulk register (HCBULKHEADED) must be 0 or
point to a valid ED before setting this bit. The HC current bulk register (HCBULKCURRENTED) must be
0 or point to a valid ED before setting this bit.
Control list enable.
The control ED list is not processed in the next 1 ms frame. The host controller driver can modify the
control ED list. If the driver removes the ED pointed to by the HC current control register
(HCCONTROLCURRENTED) from the ED list, it must update HCCONTROLCURRENTED to point to a
current ED before it reenables the control list.
Enables processing of the control ED list. The HC head control register (HCCONTROLHEADED) must
be 0 or point to a valid ED before setting this bit. The HC current control register
(HCCONTROLCURRENTED) must be 0 or point to a valid ED before setting this bit.
Isochronous enable.
Isochronous EDs are not processed. The USB1.1 host controller checks this bit every time it finds an
isochronous ED in the periodic list.
Enables processing of isochronous EDs in the next frame, if not in the current frame.
Periodic list enable.
Periodic ED lists are not processed. Periodic list processing is disabled beginning with the next frame.
Enables processing of the periodic ED lists. Periodic list processing begins in the next frame.
Control/bulk service ratio. Specifies the ratio between control and bulk EDs processed in a frame.
1 control ED per bulk ED.
2 control EDs per bulk ED.
3 control EDs per bulk ED.
4 control EDs per bulk ED.
Universal Serial Bus OHCI Host Controller
Registers
15