Hc Interrupt Enable Register (Hcinterruptenable); Hc Interrupt Enable Register (Hcinterruptenable) Field Descriptions - Texas Instruments TMS320C6747 DSP User Manual

Registers
3.5

HC Interrupt Enable Register (HCINTERRUPTENABLE)

The HC interrupt enable register (HCINTERRUPTENABLE) enables various OHCI interrupt sources to
generate interrupts to the level 2 interrupt controller. HCINTERRUPTENABLE is shown in
described in Table
31 30 29
MIE OC
R/W1S-0 R-0
15
LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing 0 has no effect); -n = value after reset
Table 6. HC Interrupt Enable Register (HCINTERRUPTENABLE) Field Descriptions
Bit Field Value
31 MIE
0
1
30 OC 0-1
29-7 Reserved 0
6 RHSC
0
1
5 FNO
0
1
4 UE
0
1
3 RD
0
1
2 SF
0
1
1 WDH
0
1
0 SO
0
1
18 Universal Serial Bus OHCI Host Controller
6.
Figure 6. HC Interrupt Enable Register (HCINTERRUPTENABLE)
Reserved
R-0
Description
Master interrupt enable. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the
corresponding bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
OHCI interrupt sources are ignored and USB1.1 host controller interrupts are not propagated to the
level 2 interrupt controller.
Allows other enabled OHCI interrupt sources to propagate to the level 2 interrupt controller.
Ownership change.
Reserved
Root hub status change. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the
corresponding bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
Root hub status change interrupts do not propagate.
When MIE is 1, allows root hub status change interrupts to propagate to the level 2 interrupt controller.
Frame number overflow. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the
corresponding bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
Frame number overflow interrupts do not propagate.
When MIE is 1, allows frame number overflow interrupts to propagate to the level 2 interrupt controller.
Unrecoverable error. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the
corresponding bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
Unrecoverable error interrupts do not propagate.
When MIE is 1, allows unrecoverable error interrupts to propagate to the level 2 interrupt controller.
Resume detected. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the corresponding
bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
Resume detected interrupts do not propagate.
When MIE is 1, allows resume detected interrupts to propagate to the level 2 interrupt controller.
Start of frame. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the corresponding bit in
the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
Start of frame interrupts do not propagate.
When MIE is 1, allows start of frame interrupts to propagate to the level 2 interrupt controller.
Write done head. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the corresponding
bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
Write done head interrupts do not propagate.
When MIE is 1, allows write done head interrupts to propagate to the level 2 interrupt controller.
Scheduling overrun. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the corresponding
bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
Scheduling overrun interrupts do not propagate.
When MIE is 1, allows scheduling overrun interrupts to propagate to the level 2 interrupt controller.
Reserved
R-0
7 6 5 4
RHSC FNO UE
R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0
www.ti.com
Figure 6 and
16
3 2 1 0
RD SF WDH SO
SPRUFM8 – June 2009
Submit Documentation Feedback