Hc Head Done Register (Hcdonehead); Hc Frame Interval Register (Hcfminterval); Hc Head Done Register (Hcdonehead) Field Descriptions; Hc Frame Interval Register (Hcfminterval) Field Descriptions - Texas Instruments TMS320C6747 DSP User Manual

Registers

3.13 HC Head Done Register (HCDONEHEAD)

The HC head done register (HCDONEHEAD) defines the physical address of the current head of the done
TD queue. HCDONEHEAD is shown in
31
15
LEGEND: R = Read only; -n = value after reset
Table 14. HC Head Done Register (HCDONEHEAD) Field Descriptions
Bit Field Value
31-4 DH 0-FFF FFFFh Physical address of the last TD that has added to the done queue. This field represents bits 31-4
3-0 Reserved

3.14 HC Frame Interval Register (HCFMINTERVAL)

The HC frame interval register (HCFMINTERVAL) defines the number of 12-MHz clock pulses in each
USB frame. HCFMINTERVAL is shown in
31 30
FIT
R/W-0
15 14 13
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. HC Frame Interval Register (HCFMINTERVAL) Field Descriptions
Bit Field
31 FIT
30-16 FSMPS
15-14 Reserved
13-0 FRAMEINTERVAL
24 Universal Serial Bus OHCI Host Controller
Figure 14
Figure 14. HC Head Done Register (HCDONEHEAD)
DH
R-0
Description
of the physical address of the top TD on the done TD queue. TDs are assumed to begin on a
16-byte aligned address, so bits 3-0 of this pointer are assumed to be 0.
A value of 0 indicates that there are no TDs on the done queue. This register is automatically
updated by the USB1.1 host controller.
0 Reserved
Figure 15
Figure 15. HC Frame Interval Register (HCFMINTERVAL)
Value Description
0-1 Frame interval toggle. The host controller driver must toggle this bit any time it changes
the frame interval field.
0-7FFFh Largest data packet. Largest data packet size allowed for full-speed packets, in bit times.
0 Reserved
0-3FFFh Frame interval. Number of 12-MHz clocks in the USB frame. Nominally, this is set to
11,999 (2EDFh) to give a 1-ms frame. The host controller driver can make minor changes
to this field to attempt to manually synchronize with another clock source.
and described in Table
DH
R-0
and described in Table
FSMPS
R/W-0
FRAMEINTERVAL
R/W-2EDFh
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14.
4 3
Reserved
R-0
15.
SPRUFM8 – June 2009
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