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3.22 HC Port 1 Status and Control Register (HCRHPORTSTATUS1)
The HC port 1 status and control register (HCRHPORTSTATUS1) reports and controls the state of
USB1.1 host port 1. HCRHPORTSTATUS1 is shown in
Figure 23. HC Port 1 Status and Control Register (HCRHPORTSTATUS1)
31
15
7
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 23. HC Port 1 Status and Control Register (HCRHPORTSTATUS1) Field Descriptions
Bit
Field
31-21
Reserved
20
PRSC
19
OCIC
18
PSSC
17
PESC
16
CSC
15-10
Reserved
9
LSDA/CPP
SPRUFM8 – June 2009
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Reserved
R-0
Reserved
R-0
5
4
PRS/SPR
R/W-0
Value
Description
0
Reserved
Port 1 reset status change. A write of 1 clears this bit; a write of 0 has no effect.
0
Port 1 port reset status bit has not changed.
1
Port 1 port reset status bit has changed.
0
Port 1 overcurrent indicator change. Because the device does not provide inputs for signaling
external overcurrent indication to the USB1.1 host controller, this bit is always 0. Overcurrent
monitoring, if required, must be handled through some other mechanism. This bit has no
relationship to the OTG controller register bits that relate to VBUS.
Port 1 suspend status change. A write of 1 clears this bit; a write of 0 has no effect.
0
Port 1 port suspend status has not changed.
1
Port 1 port suspend status has changed. Suspend status is considered to have changed only after
the resume pulse, low-speed EOP, and 3-ms synchronization delays have been completed.
Port 1 enable status change. A write of 1 clears this bit; a write of 0 has no effect.
0
Port 1 port enable status has not changed.
1
Port 1 port enable status has changed.
Port 1 connect status change. If the DR[1] bit in the HC root hub B register (HCRHDESCRIPTORB)
is set to 1 to indicate a nonremovable USB device on port 1, this bit is set only after a root hub
reset to inform the system that the device is attached. A write of 1 clears this bit; a write of 0 has no
effect.
0
Port 1 current connect status has not changed.
1
Port 1 current connect status has changed due to a connect or disconnect event. If current connect
status is 0 when a set port reset, set port enable, or set port suspend write occurs, then this bit is
set.
0
Reserved
Port 1 low-speed device attached/clear port power. This bit is valid only when port 1 current
connect status is 1. The host controller driver can write a 1 to this bit to clear the port 1 port power
status bit; a write of 0 has no effect. The USB1.1 host controller does not control external port
power using OHCI mechanisms, so, if required, USB1.1 host port power must be controlled through
other means. This bit has no relationship to the OTG controller register bits that relate to VBUS.
System software can update this register to simplify host controller driver and/or OTG driver coding.
0
Full-speed device is attached to port 1.
1
Low-speed device is attached to port 1.
Figure 23
and described in
21
20
PRSC
R/W1C-0 R/W-0 R/W1C-0 R/W1C-0 R/W1C-0
10
3
2
POCI/CSS
PSS/SPS
R/W-0
R/W-0
Universal Serial Bus OHCI Host Controller
Registers
Table
23.
19
18
17
16
OCIC
PSSC
PESC
CSC
9
8
LSDA/CPP
PPS/SPP
R/W-0
R/W-1
1
0
PES/SPE
CCS/CPE
R/W-0
R/W-0
31
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