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3.9
HC Head Control Register (HCCONTROLHEADED)
The HC head control register (HCCONTROLHEADED) defines the physical address of the head endpoint
descriptor (ED) on the control ED list. HCCONTROLHEADED is shown in
Table
10.
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. HC Head Control Register (HCCONTROLHEADED) Field Descriptions
Bit
Field
Value
31-4
CHED
0-FFF FFFFh Physical address of the head ED on the control ED list. This field represents bits 31-4 of the
3-0
Reserved
SPRUFM8 – June 2009
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Figure 10. HC Head Control Register (HCCONTROLHEADED)
CHED
R/W-0
Description
physical address of the head ED on the control ED list. EDs are assumed to begin on a 16-byte
aligned address, so bits 3-0 of this pointer are assumed to be 0. For the restrictions on physical
addresses, see
Section
0
Reserved
CHED
R/W-0
2.7.
Universal Serial Bus OHCI Host Controller
Registers
Figure 10
and described in
4
3
Reserved
R-0
16
0
21
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