Hc Head Bulk Register (Hcbulkheaded); Hc Current Bulk Register (Hcbulkcurrented); Hc Head Bulk Register (Hcbulkheaded) Field Descriptions; Hc Current Bulk Register (Hcbulkcurrented) Field Descriptions - Texas Instruments TMS320C6747 DSP User Manual

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3.11 HC Head Bulk Register (HCBULKHEADED)

The HC head bulk register (HCBULKHEADED) defines the physical address of the head endpoint
descriptor (ED) on the bulk ED list. HCBULKHEADED is shown in
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. HC Head Bulk Register (HCBULKHEADED) Field Descriptions
Bit Field Value
31-4 BHED 0-FFF FFFFh Physical address of the head ED on the bulk ED list. This field represents bits 31-4 of the physical
3-0 Reserved

3.12 HC Current Bulk Register (HCBULKCURRENTED)

The HC current bulk register (HCBULKCURRENTED) defines the physical address of the next endpoint
descriptor (ED) on the bulk ED list. HCBULKCURRENTED is shown in
Table 13.
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. HC Current Bulk Register (HCBULKCURRENTED) Field Descriptions
Bit Field Value
31-4 BCED 0-FFF FFFFh Physical address of the current ED on the bulk ED list. This field represents bits 31-4 of the
3-0 Reserved
SPRUFM8 – June 2009
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Figure 12. HC Head Bulk Register (HCBULKHEADED)
BHED
R/W-0
Description
address of the head ED on the bulk ED list. EDs are assumed to begin on a 16-byte aligned
address, so bits 3-0 of this pointer are assumed to be 0. For the restrictions on physical
addresses, see Section
0 Reserved
Figure 13. HC Current Bulk Register (HCBULKCURRENTED)
BCED
R/W-0
Description
physical address of the next ED on the bulk ED list. EDs are assumed to begin on a 16-byte
aligned address, so bits 3-0 of this pointer are assumed to be 0. For the restrictions on physical
addresses, see Section
A value of 0 indicates that the USB1.1 host controller has reached the end of the bulk ED list
without finding any transfers to process. This register is automatically updated by the USB1.1 host
controller.
0 Reserved
Figure 12
BHED
R/W-0
2.7.
BCED
R/W-0
2.7.
Universal Serial Bus OHCI Host Controller
and described in Table
4 3
Reserved
R-0
Figure 13 and described in
4 3
Reserved
R-0
Registers
12.
16
0
16
0
23