Xilinx ML505 User Manual page 40

Chapter 1: ML505/ML506/ML507 Evaluation Platform
40
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Table 1-21: CPU Trace/Debug Connection to FPGA (Cont'd)
(1)
Pin Name FPGA Pin (U1)
-
-
CPU_TDO
TRC_VSENSE
-
-
CPU_TCK
MICTOR_16
CPU_TMS
MICTOR_18
FPGA_CS0_B
(CPU_TDI)
MICTOR_20
CPU_TRST
MICTOR_22
MICTOR_23
TRC_TS1O
MICTOR_25
TRC_TS2O
MICTOR_27
TRC_TS1E
MICTOR_29
TRC_TS2E
MICTOR_31
TRC_TS3
MICTOR_33
TRC_TS4
MICTOR_35
TRC_TS5
MICTOR_37
TRC_TS6
Notes:
1. MICTOR_* pins are only available on the ML507 board. These pins are not connected on the
ML505 and ML506 boards.
www.xilinx.com
Mictor Pin (P22)
NC 9
NC 10
E7 11
- 12
NC 13
NC 14
E6 15
B18 16
U10 17
B17 18
AF21 19
B16 20
V10 21
B15 22
A23 23
AF10 24
A21 25
AF9 26
A20 27
AK9 28
A19 29
AK8 30
A18 31
AJ11 32
A16 33
AK11 34
A15 35
AD11 36
A14 37
AD10 38
ML505/ML506/ML507 Evaluation Platform
BDM Pin (J51)
1
7
9
3
4
UG347 (v3.1.1) October 7, 2009
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