Single-Ended Expansion I/O Connectors - Xilinx ML505 User Manual

R
ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
Downloaded from Elcodis.com electronic components distributor
Table 1-9: Expansion I/O Differential Connections (J4)
J4 Differential Pin Pair
Pos Neg
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64

Single-Ended Expansion I/O Connectors

Header J6 contains 32 single-ended signal connections to the FPGA I/Os. This permits the
signals on this connector to carry high-speed, single-ended data. All single-ended signals
on connector J6 are matched length traces. The V
3.3V by setting jumper J20.
expansion I/O connector.
Table 1-10: Expansion I/O Single-Ended Connections (J6)
J6 Pin
2
4
6
8
10
12
14
16
Schematic Net Name
Pos
2 HDR2_4
6 HDR2_8
10 HDR2_12
14 HDR2_16
18 HDR2_20
22 HDR2_24
26 HDR2_28
30 HDR2_32
34 HDR2_36
38 HDR2_40
42 HDR2_44
46 HDR2_48
50 HDR2_52
54 HDR2_56
58 HDR2_60
62 HDR2_64
Table 1-10 summarizes the single-ended connections on this
Schematic Net Name
HDR1_2
HDR1_4
HDR1_6
HDR1_8
HDR1_10
HDR1_12
HDR1_14
HDR1_16
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Detailed Description
FPGA Pin
Neg Pos
HDR2_2 L34
HDR2_6 K33
HDR2_10 P32
HDR2_14 T33
HDR2_18 R33
HDR2_22 U33
HDR2_26 U32
HDR2_30 V32
HDR2_34 W34
HDR2_38 Y33
HDR2_42 AF34
HDR2_46 AF33
HDR2_50 AC34
HDR2_54 AC32
HDR2_58 AC33
HDR2_62 AN32
of these signals can be set to 2.5V or
CCIO
FPGA Pin
H33
F34
H34
G33
G32
H32
J32
J34
Neg
K34
K32
N32
R34
R32
T34
U31
V33
V34
AA33
AE34
AE33
AD34
AB32
AB33
AP32
23