Zbt Synchronous Sram; Linear Flash Chips; Xilinx Xc95144Xl Cpld - Xilinx ML505 User Manual

Chapter 1: ML505/ML506/ML507 Evaluation Platform

18. ZBT Synchronous SRAM

19. Linear Flash Chips

20. Xilinx XC95144XL CPLD

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Caution!
Use caution when inserting a CompactFlash card with exposed metallic surfaces.
Improper insertion can cause a short with the traces or components on the board.
The System ACE MPU port is connected to the FPGA. This connection allows the FPGA to
use the System ACE controller to reconfigure the system or access the CompactFlash card
as a generic FAT file system. The data bus for the System ACE MPU port is shared with the
USB controller.
The ZBT synchronous SRAM (ISSI IS61NLP25636A-200TQL) provides high-speed, low-
latency external memory to the FPGA. The memory is organized as 256K x 36 bits. This
organization provides for a 32-bit data bus with support for four parity bits. The ZBT
SRAM is located under the removable LCD and is not visible in
Note:
The SRAM and FLASH memory share the same data bus.
A NOR linear flash device (Intel JS28F256P30T95) is installed on the board to provide
32 MB of flash memory. This memory provides non-volatile storage of data, software, or
bitstreams. The flash chip is 16 bits wide and shares its data bus with SRAM. The flash
memory can also be used to program the FPGA.
Note:
The reset for the AC97 Codec is shared with the reset signal for the flash memory chips and
is designed to be asserted at power-on or at system reset.
A Xilinx XC95144XL CPLD provides general-purpose glue logic for the board. The CPLD
is located under the removable LCD and is not visible in
programmed from the main JTAG chain of the board. The CPLD is mainly used to
implement level translators, simple gates, and buffers.
www.xilinx.com
Figure 1-2, page
Figure 1-2, page 15. The CPLD is
ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
R
15.