Xilinx ML505 User Manual page 51

R
ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
Downloaded from Elcodis.com electronic components distributor
Table 1-34: System Monitor Connections (Cont'd)
External Input FPGA Pin
VAUXN[5] Y34
VAUXP[5] AA34
VAUXN[6] AA33
VAUXP[6] Y33
VAUXN[7] V34
VAUXP[7] W34
VAUXN[8] V33
VAUXP[8] V32
VAUXN[9] U31
VAUXP[9] U32
VAUXN[10] T34
VAUXP[10] U33
VAUXN[11] R32
VAUXP[11] R33
VAUXN[12] R34
VAUXP[12] T33
VAUXN[13] N32
VAUXP[13] P32
VAUXN[14] K32
VAUXP[14] K33
VAUXN[15] K34
VAUXP[15] L34
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Header Pin Schematic Net Name
J6-30 HDR1_30
J6-26 HDR1_26
J4-38 HDR2_38_SM_6_N
J4-40 HDR2_40_SM_6_P
J4-34 HDR2_34_SM_15_N
J4-36 HDR2_36_SM_15_P
J4-30 HDR2_30_DIFF_3_N
J4-32 HDR2_32_DIFF_3_P
J4-26 HDR2_26_SM_11_N
J4-28 HDR2_28_SM_11_P
J4-22 HDR2_22_SM_10_N
J4-24 HDR2_24_SM_10_P
J4-18 HDR2_18_DIFF_2_N
J4-20 HDR2_20_DIFF_2_P
J4-14 HDR2_14_DIFF_1_N
J4-16 HDR2_16_DIFF_1_P
J4-10 HDR2_10_DIFF_0_N
J4-12 HDR2_12_DIFF_0_P
J4-6 HDR2_6_SM_7_N
J4-8 HDR2_8_SM_7_P
J4-2 HDR2_2_SM_8_N
J4-4 HDR2_4_SM_8_P
Detailed Description
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