Xilinx ML505 User Manual page 39

R
ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
Downloaded from Elcodis.com electronic components distributor
The JTAG debug port supports the four required JTAG signals: TCK, TMS, TDI, and TDO.
It also implements the optional TRST signal. The frequency of the JTAG clock signal can
range from 0 MHz (DC) to one-half of the processor clock frequency. The JTAG debug port
logic is reset at the same time the system is reset, using TRST. When TRST is asserted, the
JTAG TAP controller returns to the test-logic reset state.
Figure 1-7 shows a 38-pin Mictor connector that combines the CPU Trace and the CPU
Debug interfaces for high-speed, controlled-impedance signaling.
Note:
MICTOR_* pins are only available on the ML507 board. These pins are not connected on the
ML505 and ML506 boards.
TRC_TS6
TRC_TS5
TRC_TS4
TRC_TS3
TRC_TS2E
TRC_TS1E
TRC_TS2O
TRC_TS1O
MICTOR_22
MICTOR_20
2.5V
MICTOR_18
MICTOR_16
NC
TRC_VSENSE
NC
NC
TRC_CLK
NC
NC
Figure 1-7: Combined Trace/Debug Connector Pinout
Table 1-21 shows the CPU trace/debug connections from P22 to the FPGA and BDM.
Table 1-21: CPU Trace/Debug Connection to FPGA
(1)
Pin Name FPGA Pin (U1)
-
-
-
-
MICTOR_5
TRC_CLK
PC4_HALT_B
(CPU_HALT_N)
-
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Mictor 38 (P22)
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
GND, G1, G2, G3, G4, G5
Mictor Pin (P22)
NC 1
NC 2
3
NC 4
A24 5
AD9 6
W9 7
NC 8
Detailed Description
37
MICTOR_37
35
MICTOR_35
33
MICTOR_33
31
MICTOR_31
29
MICTOR_29
27
MICTOR_27
25
MICTOR_25
23
MICTOR_23
21
CPU_TRST
19
FPGA_CS0_B
17
CPU_TMS
15
CPU_TCK
13
NC
11
CPU_TDO
9
NC
7
PC4_HALT_B
5
MICTOR_5
3
NC
1
NC
UG347_06_011008
BDM Pin (J51)
11
39