Lcd Brightness And Contrast Adjustment; Gpio Dip Switches (Active-High) - Xilinx ML505 User Manual

Chapter 1: ML505/ML506/ML507 Evaluation Platform

5. LCD Brightness and Contrast Adjustment

6. GPIO DIP Switches (Active-High)

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FPGA. The programmable clock generator provides the following factory default single-
ended outputs:
•
25 MHz to the Ethernet PHY (U16)
•
14 MHz to the audio codec (U22)
•
27 MHz to the USB Controller (U23)
•
33 MHz to the Xilinx System ACE CF (U2)
•
33 MHz, 27 MHz, and a differential 200 MHz clock to the Xilinx FPGA
If users change the factory default configuration of the clock generator chip, the related
reference design material might not work as designed. Instructions for returning the
IDT5V9885 to the factory default configuration are provided in
"Programming the IDT Clock Chip."
Table 1-4: Oscillator Socket Connections
Reference
Clock Name
Designator
X1 USER_CLK
U8 CLK_33MHZ_FPGA
U8 CLK_27MHZ_FPGA
U8 CLK_FPGA_P
U8 CLK_FPGA_N
Turning potentiometer R87 adjusts the image contrast of the character LCD. The
potentiometer should be turned with a screwdriver.
Eight general-purpose (active-High) DIP switches are connected to the user I/O pins of the
FPGA. Table 1-5 summarizes these connections.
Table 1-5: DIP Switch Connections (SW4)
SW4
GPIO_DIP_SW1
GPIO_DIP_SW2
GPIO_DIP_SW3
GPIO_DIP_SW4
GPIO_DIP_SW5
GPIO_DIP_SW6
GPIO_DIP_SW7
GPIO_DIP_SW8
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FPGA Pin
AH15 100 MHz single-ended
AH17 33 MHz single-ended
AG18 27 MHz single-ended
L19 200 MHz differential pair (pos)
K19 200 MHz differential pair (neg)
FPGA Pin
U25
AG27
AF25
AF26
AE27
AE26
AC25
AC24
ML505/ML506/ML507 Evaluation Platform
Appendix B,
Description
UG347 (v3.1.1) October 7, 2009
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