Appendix B: Programming The Idt Clock Chip; Overview; Downloading To The Ml50X Board - Xilinx ML505 User Manual

Programming the IDT Clock Chip

Overview

Downloading to the ML50x Board

ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
Downloaded from Elcodis.com electronic components distributor
R
The ML50x evaluation boards feature an Integrated Device Technology (IDT) 3.3V
EEPROM Programmable Clock Generator that is pre-programmed at the factory. In the
event the chip programming is changed, the instructions in this appendix show how to
return the clock chip to its factory default settings using the following equipment:
•
Xilinx download cable
•
JTAG flying wires
1. Connect a Xilinx download cable to the board using flying leads connected to jumper
J3 (Figure B-1).
Click Start → iMPACT.
2.
3. Click Boundary Scan.
4. Right-click Add Xilinx Device...
5. Locate the SVF file (ML50X_clock_setup.svf in the example shown in
page 58) and click Open.
Note:
The ML50X_clock_setup.svf file is available on the ML50x product page.
6. Right-click on the device and select Execute XSVF/SVF.
CLK Prog
J3
TMS
1
TDI
TDO
TCK
GND
3.3V
UG347_apdx_a_02_020807
Figure B-1: J3 IDT5V9885 JTAG Connector
www.xilinx.com
Appendix B
Figure B-2,
57