Furuno FAR-2107 Series Service Manual page 378

U21 HD6417750RF240(SH4) MAIN CPU
U22 EDS1232AATA-75
Note
U48 MBM29DDL640E90TN
U47 MBM29DDL640E90TN
U74 HD6417750RF240(SH4) ARPA CPU
U56 EDS1232AATA-75
U19 HD6417750RF240(SH4) DRW CPU
U9 EDS1232AATA 75
U16 EDS1232AATA-75
U46 XC2V500 4FG456C
Note
U54 XC18V04VD044C
U13 XC2V250 4FG256C
Note
U6 XC18V04VD044C
U12 XC2V500 4FG456C
Note
U15 XC18V04VD044C
U3 EOS1232AATA 75
U2 K4S561632D TC75
U1 K4S561632D TC75
U28 IDT70V25S25PF
Note:
Since the saving of FPGA is transferred to U48 on and after the SPU board Ver-22,
U6, U15 and U54 are eliminated.
Device model
128 M SDRAM
64 M Flash ROM
64 M Flash ROM
128 M SDRAM
128 M SDRAM
128 M SDRAM
SPU FPGA
ISP PROM
(In System Programming)
DRW FPGA
ISP PROM
(In System Programming)
Echo FPGA
ISP PROM
(In System Programming)
128 M SDRAM
256 M SDRAM
256 M SDRAM
Dual port RAM
Data processing, control and operation
Memory for MAIN CPU. When the power
is on, the program from U48 is
decompressed and starts MAIN CPU
- MAIN, ARPA, DRW CPU programs are
compressed and stored.
Note: FPGA program is added on and
- Decompression is performed by MAIN
CPU
For backup of signal values and trail
ARPA processing unit
Memory for ARPA CPU work
Decompress the program from U48 at the
time of power-ON and starts ARPA CPU
DRW CPU, drawing, reading, address
generation
Memory for DRW CPU work
Decompress the program from U48 at the
time of power-ON and starts DRW CPU
Image memory for graphics
Signal processing, ARPA data processing
FPGA
SPU FPGA program
Includes the U46 (FPGA) circuit written on
it. Program is sent to FPGA at the time of
power-ON and starts FPGA
Echo processing, drawing,
displaying FPGA
DRW FPGA program
Includes the U13 (FPGA) circuit written on
it. Program is sent to FPGA at the time of
power-ON and starts FPGA
Graphics processing FPGA
ECHO FPGA program
Includes the U12 (FPGA) circuit written on
it. Program is sent to FPGA at the time of
power-ON and starts FPGA
Memory for displaying
Memory for surface correlation
Memory for trail
Dual port RAM between DRW CPU and
MAIN CPU
7-34
7.3 Processor Unit: RPU-013
Table 7.3.2 Major devices
Application
after the SPU board Ver-22