Nintendo GAME BOY Programming Manual page 69

1.8.4 New DMA Control Registers: CGB only
ADDRESS
NAME
HDMA1
FF51
HDMA2 FF52
HDMA3
FF53
HDMA4 FF54
HDMA5
FF55
Horizontal blanking
DMA
General-purpose DMA
Note: These registers cannot be written to in DMG mode.
BIT
7 6 5 4
7 6 5 4
Combined with HDMA1, specifies the upper 12 bits of the transfer source area
(0x000X-0x7FFX or 0xA00X-0xDFFX)
7 6 5 4
7 6 5 4
Combined with HDMA3, specifies the upper 12 bits of the transfer destination area
(800Xh-9FFXh)
7 6 5 4
Value of 1 written:
After 1 is written, horizontal blanking DMA transfer is started from the
first horizontal blanking period.
(DMA should always be started with LCDC on and value other than 00
for STAT mode.)
* When a value of 0 has been subsequently written, DMA transfer
stops beginning with the next horizontal blanking period.
Value of 0 written (the following applies only when the bit is already 0):
General-purpose DMA starts
(DMA should be started with LCDC off or during a horizontal blanking
period. Ensure that the transfer period does not overlap with STATE mode
settings of 10 or 11.)
* Only input of a reset signal can halt a general-purpose DMA transfer in
progress.
3 2 1 0
W
3 2 1 0
W
3 2 1 0
W
3 2 1 0
W
3 2 1 0
R/W
(n)
Horizontal Blanking DMA
No. of lines to transfer = (n + 1)
Total no. of bytes to transfer = 16 x (n+1)
(Max = 2,048 bytes)
General-purpose DMA
Total no. of bytes transfer = 16 x (n +1)
(Max = 2,048)
69
Chapter 2: Display Functions
Specifies higher-order transfer source
address
00h-7Fh(program ROM)
A0h-DFh (external and unit working RAM)
Specifies lower-order transfer source
address
0Xh-FXh
Specifies higher-order transfer
destination
address
00h-1Fh
Specifies lower-order transfer
destination
address
0Xh-FXh
Transfer start and number of bytes to
transfer