Nintendo GAME BOY Programming Manual page 23

Register
P1
SC
TIMA
TAC
IE
LCDC
SCY
SCX
LYC
WY
W
Interrupt Enable (IE)
Standby Modes
The standby functions are HALT mode, which halts the system clock, and STOP mode,
which halts oscillation (source oscillation).
HALT Mode
Game Boy switches to HALT mode when a HALT instruction is executed.
The system clock and CPU operation halt in this mode. However, operation of source
oscillation circuitry between terminals CK1 and CK2 continues. Thus, the functions that do
not require the system clock (e.g,, DIV, SIO, timer, LCD controller, and sound circuit)
continue to operate in this mode.
HALT mode is canceled by the following events, which have the starting addresses
indicated.
1) A LOW signal to the /RESET terminal
Starting address: 0000h
2) The interrupt-enable flag and its corresponding interrupt request flag are set
IME = 0 (Interrupt Master Enable flag disabled)
Starting address: address following that of the HALT instruction
IME = 1 (Interrupt Master Enable flag enabled)
Starting address: each interrupt starting address
STOP Mode
Game Boy switches to STOP mode when a STOP instruction is executed.
The system clock and oscillation circuitry between the CK1 and CK2 terminals are halted in
this mode. Thus, all operation is halted except that of the SI0 external clock. STOP mode is
canceled by the following events, and started from the starting address.
3) A LOW signal to the /RESET terminal
Starting address: 0000h
4) A LOW signal to terminal P10, P11, P12, or P13
Starting address: address following that of STOP instruction
When STOP mode is canceled, the system clock is restored after 217 times the oscillation
clock (DMG: 4 MHz, CGB: 4 MHz/8 MHz), and the CPU resumes operation.
When STOP mode is entered, the STOP instruction should be executed after all interrupt-
enable flags are reset, and meanwhile, terminals P10-P13 are all in a HIGH period.
Status
0
0
0
0
0
$83 BG/OBJ ON, LCDC OPERATION
0
0
0
0
0
DI
23
Chapter 1: System
Stack: FFFEh