Nintendo GAME BOY Programming Manual page 21

Game Boy Color CPU
/RD/WR/CS
/MRD
Timing
/MWR
Control
/CS1
A0-A15
MA0-MA12
RA0,RA1
PHI
CK1
C. G
CK2
SCK
SI
SIO
SO
Infrared
Comm Port/
R0-R4
General
Purpose
Port
VDD3
VDD5
GND
MD8-MD15
MD0-MD7 D0-D7
....
Data Buffer
CPU Core
PC
SP
A F
B C
D E
H L
Divider
DIV
Timer
TIMA TMA TAC
OAM RAM
40x28 bit
LCD Display RAM Interface
TEST0-TEST2
21
/NMI P00-P03
Keyport
Interrupt
Controller
Sound 1
NR10-NR14
Sound 2
NR20-NR23
Sound 3
NR30-NR33
Sound 4
NR40-NR42
Waveform
RAM
32x4
Palette RAM
LCD Controller
(DMA Controller)
/MCS0,/MCS1 PSMO1
Chapter 1: System
P10-P13
RAM
127 bytes
ROM
2 Kbytes
SO1
SO2
VIN
Sound
Control
NR50-NR52
LDR0-LDR5
LDG0-LDG5
LDB0-LDB5
DCK
SPL
LP
PS
SPS
CLS
MOD
REVC
M1
/RESET
PSMO0