Nintendo GAME BOY Programming Manual page 270

Game Boy Programming Manual
Register Address
BGP FF47
BG Palette
Data
OBP0 FF48
OBJ palette
data 0
OBP1 FF49
OBJ palette
data 1
WY FF4A
Window y-
coordinate
WY FF4B
Window x-
coordinate
KEY1 FF4D Current
speed:
CPU speed 0:
switching Normal 1:
Double-
speed
VBK FF4F
VRAM bank
specification
HDMA1 FF51
Higher-order
address of
HDMA transfer
source
HDMA2 FF52
Lower-order
address of
HDMA transfer
source
HDMA3 FF53
Higher-order
address of
HDMA transfer
destination
D7 D6 D5
Palette data for Palette data for
character dot data character dot data
11 in DMG mode. 10 in DMG mode.
Palette data for Palette data for
character dot data character dot data
11 in DMG mode. 10 in DMG mode.
Palette data for Palette data for
character dot data character dot data
11 in DMG mode. 10 in DMG mode.
D4 D3 D2
Palette data for
character dot
data 01 in DMG
mode.
Palette data for
character dot
data 01 in DMG
mode.
Palette data for
character dot
data 01 in DMG
mode.
270
D1 D0 Comment
Palette data for W
character dot data
00 in DMG mode.
Palette data for W
character dot data When attribute
00 in DMG mode. bit 4 is 0.
Palette data for W
character dot data When attribute
00 in DMG mode. bit 4 is 1.
R/W
0 – 143
Top edge when
WY=0
R/W
7 – 165
Left edge when
WY=7
Enable R/W Switch by
speed setting bit 0 to 1
switching and issuing a
STOP
instruction
Bank R/W
0: Bank 0 Bank 0 selected
1: Bank 1 immediately
after a reset
signal.
W
00h – 7Fh (ROM)
A0h – DFh
(WRAM)
W
0Xh – FXh
W
00h – 1Fh