Mbc5 - Nintendo GAME BOY Programming Manual

3.2.2 Condensation (Required)
MBC3 uses a crystal oscillator for its clock counter operation, and condensation on the oscillator
may halt its oscillation, preventing the clocks from counting up. Once the condensation
disappears, the clocks will resume counting up from where they stopped. However, please ensure
that the counter stoppage does not result in a loss of program control.
3.2.3 Control Register Initialization (Required)
Although control registers 0-3 are initialized (see Section 3.2, Description of Registers) when the
Game Boy power is turned on, they are not initialized by a hard reset of Super NES when Super
Game Boy is used. Therefore, please be sure to implement a software reset of these registers.
3.2.4 Clock Counter Registers (Required)
When commercial GB software that use MBC3 are shipped from the factory, the values of the
clock counter registers are undefined. Therefore, please ensure that these registers are initialized.

3.3 MBC5

3.3.1 Memory Image (Required)
If a memory device is used that uses less than the maximum amount of memory available (ROM:
64 Mbits; RAM: 1 Mbit) , a memory image is generated for the empty bank area. Therefore,
please do not develop software that uses an image, because it may cause failures.
3.3.2 Specifying External Sound Input (VIN) (Required)
Always use the sound control register (NR50) with bits 7 and 3 (VIN function OFF) set to 0.
Because the VIN terminal is used in development flash ROM cartridges, using the register with
VIN set to ON will produce sound abnormalities.
3.3.3 Disabling Vibration Using the SGB, SGB2, or 64GB Pak (Recommended)
When MBC5 with rumble feature is used by SGB, SGB2, or the 64GB Pak, vibration should be
turned off by the program to prevent failures caused by a faulty connection. For methods of
recognizing SGB and SGB2, see Chapter 6, section 4.2, Recognizing SGB. With the 64GB Pak,
vibration is controlled by the N64 software. Therefore, N64 software programs that support MBC5
should not write data to bit 3 of the RAM bank register.
3.3.4 Disabling Vibrations for Resets and Pauses (Recommended)
Vibration should be halted during resets and pauses.
When power is turned on, the hardware should not be vibrated until some input is received from
the controller.
Appendix 1: Programming Cautions
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