Cpu Functions (Common To Dmg/Cbg ) - Nintendo GAME BOY Programming Manual

Game Boy Programming Manual
2.5 CPU Functions (Common to DMG/CGB )
This section describes the CPU functions that have been enhanced in CGB. Functions that are
identical in DMG and CGB are described in Section 2.4, CPU Functions (Common to DMG/CGB ).
CPU functions not available in DMG are described in Section 2.6, CPU Functions (CGB only).
2.5.1 Serial Cable Communication
Note: In DMG mode, bit 1 of the SC register is set to 1 and cannot be changed,
but the transfer speed is fixed at 8 KHz.
Serial I/O (SIO) is controlled by the SB and SC registers.
The lowest bit (SC0) of the SC register can be used to select shift clock to be either the external
clock from the SCK terminal or the internal shift clock.
Sending and receiving occur simultaneously with a serial transfer.
If the data to be sent is set in the SB register and the serial transfer is then started, the received
data is set in the SB register when the transfer is finished.
Serial transfer procedure:
1
The data is set in the SB register.
2
Setting the highest SC register bit (SC 7) to 1 starts the transfer.
3
The 3-bit counter is reset and after 8 counts of the shift clock, the transfer is performed
until overflow occurs.
4
SC7 is reset.
5 If the serial transfer completion interrupt is enabled, the CPU is interrupted.
When the shift clock goes low, the contents of the SB register are shifted leftward and the data is
output from the highest bit. When the shift clock goes high, input data from the SIN terminal are
output to the lowest bit of the SB register.
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