Mbc5; Overview; Registers; Memory Map - Nintendo GAME BOY Programming Manual

Game Boy Programming Manual

4. MBC5

4.1 Overview

Supports CGB double-speed mode.
MBC5 can use up to 64 Mbits of ROM (512 banks of 128 bits each) and
1 Mbit of RAM (16 banks of 64 Kbits each).
Upwardly compatible with MBC1.

4.2 Registers

Name
RAMG
ROMB 0
ROMB 1
RAMB

4.3 Memory Map

Maximum of 1
Mbit
Set by RAMB register.
Accessible only
when RAMG register
is 0Ah.
Addresses (hex)
CPU Address
RAM
FFFFh
Highest bank,
0Fh
E000h
: :
: :
C000h
Bank 01h
A000h
Bank 00h
8000h
Empty
(no image)
6000h
5000h
RAMB
4000h
ROMB1
3000h
ROMB0
2000h
RAMG
0000h
Writing
During a write, data is written to the bank control registers at
CPU addresses 0000h-7FFFh. During a read, the contents of
ROM are read from these addresses.
0000-1FFF
2000-2FFF
3000-3FFF
4000-5FFF
Unit
Registers
Internal
Working
RAM
External
Expansion
Working RAM
Display
RAM
Bank Switching
Area
Bank 0x00 - Bank
0x1FF
(Default bank 0x01)
Program Residence
Area
Fixed at
Bank 0x00
Reading
224
ROM
Highest bank,
1FFh
: :
: :
Up to 64 Mbits
Set by the
: :
ROMB0,
ROMB1
registers
: :
: :
: :
Bank 1
Bank 0