System Reset; Figure 10. Pvd Threshold - ST STM32F7 Series Application Notes

Power supplies
A PVDO flag is available, in the PWR power control/status register (PWR_CSR1), to
indicate if V
to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers.
The PVD output interrupt can be generated when V
and/or when V
edge configuration. As an example the service routine could perform emergency shutdown
tasks.
1.3.3

System reset

A system reset sets all the registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the backup domain (see
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset).
2. Window watchdog end of count condition (WWDG reset).
3. Independent watchdog end of count condition (IWDG reset).
4. A software reset (Software reset).
5. A low-power management reset.
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is higher or lower than the PVD threshold. This event is internally connected
DD
rises above the PVD threshold depending on EXTI line16 rising/falling
DD

Figure 10. PVD threshold

DocID027559 Rev 5
drops below the PVD threshold
DD
Figure
AN4661
11).