Programmable Voltage Detector (Pvd); System Reset; Figure 4. Pvd Thresholds - ST STM32F10 Series Application Note

AN2586 - Application note
1.3.2

Programmable voltage detector (PVD)

You can use the PVD to monitor the V
selected by the PLS[2:0] bits in the Power control register (PWR_CR).
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate
whether V
EXTI Line16 and can generate an interrupt if enabled through the EXTI registers. The PVD
output interrupt can be generated when V
V rises above the PVD threshold depending on the EXTI Line16 rising/falling edge
DD
configuration. As an example the service routine can perform emergency shutdown tasks.
Figure 4.
1.3.3

System reset

A system reset sets all registers to their reset values except for the reset flags in the clock
controller CSR register and the registers in the Backup domain (see
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset)
2. window watchdog end-of-count condition (WWDG reset)
3. Independent watchdog end-of-count condition (IWDG reset)
4. A software reset (SW reset)
5. Low-power management reset
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR.
is higher or lower than the PVD threshold. This event is internally connected to
DD
PVD thresholds
V
DD
PVD output
power supply by comparing it to a threshold
DD
drops below the PVD threshold and/or when
DD
PVD threshold
Power supplies
100 mV
hysteresis
ai14365
Figure 1).
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