Quadrature Serial Parallel Interface (Quad-Spi) - ST STM32F7 Series Application Notes

Recommended PCB routing guidelines for STM32F7 Series devices
Interface signal layout guidelines:
•
Reference the plane using GND or PWR (if PWR, add 10nf stitching cap between PWR
and GND
•
Trace the impedance: 50Ω ± 10%
•
The maximum trace length should be below 120mm. If the signal trace exceeds this
trace-length/speed criterion, then a termination should be used
•
Reduce the crosstalk, place data tracks on the different layers from the address and
control lanes, if possible. However, when the data and address/control tracks coexist
on the same layer they must be isolated from each other by at least 5 mm.
•
Match the trace lengths for the data group within ± 10 mm of each other to diminish the
skew. Serpentine traces (back and forth traces in an "S" pattern to increase trace
length) can be used to match the lengths.
•
Placing the clock (SDCLK) signal on an internal layer, minimizes the noise (EMI).
Route the clock signal at least 3x of the trace away from others signals. Use as less
vias as possible to avoid impedance change and reflection. Avoid using serpentine
routing.
•
Match the clock traces to the data/address group traces within ±10mm.
•
Match the clock traces to each signal trace in the address and command groups to
within ±10mm (with maximum of <= 20mm).
•
Trace the capacitances:
–
–
8.4.3

Quadrature serial parallel interface (Quad-SPI)

Interface connectivity
The Quad-SPI is a specialized communication interface targeting single, dual or Quad-SPI
FLASH memories. The Quad-SPI interface is a serial data bus interface, that consists of a
clock (SCLK), a chip select signal (nCS) and 4 data lines (IO[0:3]).
Interface signal layout guidelines
•
Reference the plane using GND or PWR (if PWR, add 10nf stitching cap between PWR
and GND
• Trace the impedance: 50Ω ± 10%
•
The maximum trace length should be below 120mm. If the signal trace exceeds this
trace-length/speed criterion, then a termination should be used
•
Avoid using multiple signal layers for the data signal routing.
•
Route the clock signal at least 3x of the trace away from other signals. Use as less vias
as possible to avoid the impedance change and reflection. Avoid using a serpentine
routing.
•
Match the trace lengths for the data group within ± 10 mm of each other to diminish
skew. Serpentine traces (back and forth traces in an "S" pattern to increase trace
length) can be used to match the lengths.
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At 3.3 V keep the trace within 20 pF with overall capacitive loading (including Data,
Address, SDCLK and Control) no more than 30pF.
At 1.8 V keep the trace within 15 pF with overall capacitive loading (including Data,
Address, SDCLK and Control) no more than 20pF.
DocID027559 Rev 5
AN4661