Figure 13. Nrst Circuitry Timing Example - ST STM32F7 Series Application Notes

Power supplies
The supply ranges which never go below 1.8V minimum should be better managed by the
internal circuitry (no additional component needed, thanks to the fully embedded reset
controller).
When the internal reset is OFF, the following integrated features are no more supported:
•
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
•
The brownout reset (BOR) circuitry must be disabled.
•
The embedded programmable voltage detector (PVD) is disabled.
•
V
BAT
All the packages, except for the LQFP64 and the LQFP100, allow to disable the internal
reset through the PDR_ON signal when connected to V
20/54
functionality is no more available and V

Figure 13. NRST circuitry timing example

DocID027559 Rev 5
pin should be connected to V
BAT
.
SS
AN4661
.
DD