External Clock (Lse Bypass); External Crystal/Ceramic Resonator (Lse Crystal); Clock Security System (Css) - ST STM32F7 Series Application Notes

Clocks
The LSE oscillator includes new modes and has a configurable drive using the LSEDRV
[1:0] in RCC_BDCR register:
•
00: Low drive.
•
10: Medium low drive.
•
01: Medium high drive.
•
11: High drive.
The LSERDY flag in the RCC backup domain control register (RCC_BDCR) indicates if the
LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released
until this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock
interrupt register (RCC_CIR).
3.2.1

External clock (LSE bypass)

In this mode, an external clock source must be provided. It must have a frequency up to
1 MHz. The user selects this mode by setting the LSEBYP and LSEON bits in the RCC
backup domain control register (RCC_BDCR). The external clock signal (square, sinus or
triangle) with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin
should be left HI-Z. See
3.2.2

External crystal/ceramic resonator (LSE crystal)

The LSE crystal is a 32.768 kHz low-speed external crystal or ceramic resonator. It has the
advantage of providing a low-power, but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The resonator and the load capacitors have to be connected as close as possible to the
oscillator pins in order to minimize the output distortion and startup stabilization time. The
load capacitance values must be adjusted according to the selected oscillator.
3.3

Clock security system (CSS)

The clock security system can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
•
If a failure is detected on the HSE clock, this oscillator is automatically disabled, a clock
failure event is sent to the break inputs of advanced-control timers TIM1 and TIM8, and
an interrupt is generated to inform the software about the failure (clock security system
interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to
the Cortex
•
If the HSE oscillator is used directly or indirectly as the system clock (indirectly
meaning that it is directly used as PLL input clock, and that PLL clock is the system
clock) and a failure is detected, then the system clock switches to the HSI oscillator and
the HSE oscillator is disabled.
•
If the HSE oscillator clock was the clock source of PLL used as the system clock when
the failure occurred, PLL is also disabled. In this case, if the PLLI2S or PLLSAI was
enabled, it is also disabled when the HSE fails.
26/54
Figure 18.
®
-M7 NMI (non-maskable interrupt) exception vector.
DocID027559 Rev 5
AN4661