G0 G1 Select Register - National Instruments PCI E Series Programmer's Manual

G0 G1 Select Register

The G0 G1 Select Register contains 8 bits that control the logical DMA selection for the two
general purpose counter timer resources. The contents of this register are cleared upon power
up and after a reset condition.
Address:
Type:
Word Size:
Bit Map:
7 6
GPCT1 D GPCT1 C
Bit
7–4
3–0
© National Instruments Corporation
Base address + 0B (hex)
Write-only
8-bit
5 4
GPCT1 B GPCT1 A
Name Description
GPCT1 <D..A> General Purpose Counter Timer 1 Logical Channel C
through A—These four bits select the MITE logical
channels that the GPCT1 uses. You can only set one of
these bits at a time.
GPCT0 <D..A> General Purpose Counter Timer 0 Logical Channel C
through A—These four bits select the MITE logical
channels that the GPCT1 uses. You can only set one of
these bits at a time.
Chapter 3
3 2
GPCT0 D GPCT0 C
3-23
Register Map and Descriptions
1 0
GPCT0 B GPCT0 A
PCI E Series RLPM