Dma Programming; Figure 4-2. Dma Structure - National Instruments PCI E Series Programmer's Manual

DMA Programming

Analog
Input
Analog
Output
GPCT0
GPCT1
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they determine if the pending interrupt belongs to their device. If it does
not, the ISR must pass control to the next ISR in the chain.
In order to determine if a PCI E Series board has a pending interrupt do the
following:
1. Perform a 32 bit memory read from BAR0 + 0x14.
2. Check the status of bit 31 (highest order bit in the register). If this bit
is high the PCI E Series board is currently asserting an interrupt.
You can program your PCI E Series board so that the analog input, analog
output, or general purpose counter/timers can generate DMA requests
under appropriate circumstances. There are four logical DMA
channels—A, B, C, and D.
Each logical channel, in turn, can service either analog input, analog
output, or the general-purpose counter/timers. You must program the AO
AI Select Register (address 0x09) and the G0G1 Select Register (address
0x0B) to assign particular logical channels to either AI, AO, or GPCTs.
Figure 4-2 shows the three-stage DMA structure.
Logical
DMA
Channel A
Logical
DMA
Channel B
Logical
DMA
Channel C
Logical
DMA
Channel D

Figure 4-2. DMA Structure

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Chapter 4 Programming
PCI E Series RLPM