Calibration; About The Eeprom - National Instruments PCI E Series Programmer's Manual

Register-level programmer manual, multifunction i/o boards for pci bus computers, register-level
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Calibration

About the EEPROM

© National Instruments Corporation
This chapter explains how to calibrate the analog input and output sections
of the PCI E Series boards by reading calibration constants from the
EEPROM and writing them to the calibration DACs. This chapter also
explains how to generate the calibration constants using NI-DAQ.
All PCI E Series boards are factory calibrated before shipment, and the
resulting calibration constants are stored in the EEPROM. Because the
calibration DACs have no memory capability, they do not retain calibration
information when the computer is turned off. Therefore, they must be
reloaded every time the computer is turned on, and the most straightforward
method is to copy these values from the EEPROM. In addition to the
factory calibration constants, new calibration constants can be generated in
the field through the use of the NI-DAQ calibration function call.
Generating new constants results in a more accurate calibration for the
actual environment in which the board is used.
The EEPROM is used to store all non-volatile information about the board,
including the factory and user calibration constants. The PCI E Series
boards use a XICOR X25040 EEPROM, which is 512 by 8 bits in size and
has a serial interface. The signals used to interface to the EEPROM are
clock, data in, data out, and chip select.
The Serial Command Register has three bits—SerClk (bit 0), SerData
(bit 1), and EEPROMCs (bit 2)—that are connected to the EEPROM clock,
data in, and chip select pins, respectively. PROMOut (bit 0) of the Status
Register is connected to the EEPROM data out pin.
The format for reading from the EEPROM is very straightforward. The
basic read cycle consists of shifting a 7-bit instruction and 9-bit address into
the EEPROM, then shifting an 8-bit data out of the EEPROM. The timing
diagram for the read cycle is shown in Figure 5-1.
The EEPROM interface is relatively slow compared to the PCI bus. In order
to meet the timing specifications of the EEPROM, you must double write
5-1
5
PCI E Series RLPM

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