Serial Command Register - National Instruments PCI E Series Programmer's Manual

Chapter 3 Register Map and Descriptions

Serial Command Register

The Serial Command Register contains six bits that control PCI E Series serial EEPROM and
DACs. The contents of this register are cleared upon power up and after a reset condition.
Address:
Type:
Word Size:
Bit Map:
7 6
Reserved Reserved
Bit
7–6
5
4
3
2
1
0
PCI E Series RLPM
Base address + 0D (hex)
Write-only
8-bit
5 4
SerDacLd2 SerDacLd1
Name Description
Reserved Reserved—Always write 0 to these bits.
SerDacLd2 Serial DAC Load2—This bit is used to load the third set of
serial DACs with the serial data previously shifted into the
DACs.
SerDacLd1 Serial DAC Load1—This bit is used to load the second set
of serial DACs with the serial data previously shifted into
the DACs.
SerDacLd0 Serial DAC Load0—This bit is used to load the first set of
serial DACs with the serial data previously shifted into the
DACs.
EEPromCS EEPROM Chip Select—This bit controls the chip select of
the onboard EEPROM used to store calibration constants.
When EEPromCS is set, the chip select signal to the
EEPROM is enabled.
SerData Serial Data—This bit is the data for the onboard serial
devices—the calibration EEPROM and the serial DACs.
This bit should be set to the desired value prior to the
active write to the SerClk bit.
SerClk Serial Clock—This bit is the clock input to the onboard
serial devices. In order to access these devices, this bit is
used to clock data in or out as appropriate. See Chapter 5,
Calibration, for more information.
3 2
SerDacLd0 EEPromCS
3-4
1
SerData SerClk
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