Configuration Memory Low Register - National Instruments PCI E Series Programmer's Manual

Configuration Memory Low Register

The Configuration Memory Low Register works with the Configuration Memory High
Register to control the input channel selection multiplexers, gain, range, and mode settings.
The values written to these registers are placed into the Configuration Memory, which is
sequenced through during an acquisition. This register contains seven of these bits. The
contents of the Configuration Memory are emptied by a control register in the DAQ-STC.
Address:
Type:
Word Size:
Bit Map:
15 14
LastChan Reserved
7 6
Reserved Reserved
Bit
15
14–13,
11–10,
7–3
12
9
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Base address + 10 (hex)
Write-only
16-bit
13 12
Reserved GenTrig
5 4
Reserved Reserved
Name Description
LastChan Last Channel—This bit should be set in the last entry of
the scan sequence loaded into the channel configuration
memory. More than one occurrence of the LastChan bit is
possible in the configuration memory list for the
interval-scanning mode. For example, there can be
multiple scan sequences in one memory list.
Reserved Reserved—Always write 0 to these bits.
GenTrig General Trigger—This bit synchronizes actions in the
DAQ-STC with the scan list. When this bit is set, an active
low trigger pulse is sent into the RTSI_BRD0 input of the
DAQ-STC during the CONVERT signal. This trigger is
used at the application level and can perform such actions
as time stamping and starting waveform generation.
DitherEn Dither Enable—This bit controls the dither circuitry
feeding the analog input. If this bit is set, approximately
±0.5 LSB of white Gaussian noise is added to the input
signal. This bit is reserved on the PCI-MIO-16XE-50,
Chapter 3
11 10
Reserved Reserved
3 2
Reserved Gain2
3-9
Register Map and Descriptions
9 8
DitherEn Unip/Bip
1 0
Gain1 Gain0
PCI E Series RLPM