Waveform Generation - National Instruments PCI E Series Programmer's Manual

Chapter 2 Theory of Operation
Register. This action will store the value in the first buffer of the DAC. If
the DAQ-STC is programmed for immediate updating mode, the value will
also be applied to the analog output. If the DAQ-STC is programmed for
timed updating mode, the appropriate update signal, LDAC0* or LDAC1*,
must be asserted by writing to the appropriate DAQ-STC register.

Waveform Generation

The timing engine in the DAQ-STC can be used for waveform generation,
where the update signals connected to the DACs can be generated at precise
intervals. In this model, the DAQ-STC will generate the update signals and
then transfer the data values for the next update to the first buffer of
the DACs.
The update interval counter (UI) is 24 bits wide and generates the update
pulses. These update pulses can be routed to the DACs. The update counter
(UC) is 24 bits wide and counts the number of updates. The value loaded
into this counter defines a buffer. The buffer counter (BC) determines how
many times a buffer should be repeated. These counters define an analog
output sequence.
The DAQ-STC will transfer the data values for the next update after each
update pulse. This data transfer will be from the analog output FIFO. Some
of the boards have large 2 kword FIFOs and some have 512 word FIFOs;
others are zero-deep virtual FIFOs. The large FIFOs are true FIFOs, where
data can be written to the FIFOs as long as they are not full, and can be read
from when they are not empty. In this case, the DAQ-STC will transfer the
data from the FIFO to the DACs when the FIFO is not empty. If the FIFO
is empty, the DAQ-STC will delay the transfer until more data is written
into the FIFO.
The zero-deep virtual FIFOs are not true FIFOs, but they do provide a
software compatible method for waveform generation. When the
DAQ-STC generates an update signal and is ready to transfer data, the
board will clear the FIFO full flag. This FIFO full flag can be used by
interrupts or DMA to transfer data to the virtual FIFO. The virtual FIFO
will not actually buffer the data, instead it will transfer it directly to the first
buffer of the destination DAC. After the data has been transferred, the board
will set the FIFO full flag, indicating that no more data is required. Note
that the half-full and empty flags do not provide useful information for data
transfer and should not be used.
The large FIFOs can also be used to generate repetitive waveforms at
very high speeds and without using any bus bandwidth. The FIFOs can be
loaded with the desired waveform and the DAQ-STC can be programmed
© National Instruments Corporation 2-23 PCI E Series RLPM