Figure 4-1. Analog Trigger Structure - National Instruments PCI E Series Programmer's Manual

Chapter 4 Programming
Analog
Input
Channels
PFI0/TRIG1
PCI E Series RLPM
+
PGIA
-
Mux
Int/Ext Trig

Figure 4-1. Analog Trigger Structure

To set the low and high analog thresholds, the DACs must be written with
appropriate values. The protocol for writing to these DACs is described in
Chapter 5, Calibration.
The function
Analog_Trigger_Control
a mode of operation. When analog trigger is enabled, the analog trigger
signal takes over the PFI0/TRIG1 slot, and this pin can no longer be used
as an input. For more information about this function, see the Programming
Analog Trigger section of Chapter 10 in the DAQ-STC Technical
Reference Manual.
The following example is written for the PCI-MIO-16E-1,
PCI-MIO-16E-4, and PCI-6071 boards, which use 8-bit CALDAC for the
analog trigger; the PCI-6052E, PCI-MIO-16XE-10, PCI-6031E,
PCI-6032E, and PCI-6033E use an AD8522, which contains two 12-bit
DACs. The PCI-MIO-16XE-50 does not support analog triggering. The
write cycle for the 8-bit and 12-bit DACs is illustrated in Chapter 5 of this
manual in the Calibration DACs
mode and the PGIA as the triggering source. The low value is set to be 0 V,
ADC
High
Comparator
Serial
DAC
Low
Comparator
Serial
DAC
Analog_Trigger_Drive
enables analog triggering to set
section. The example uses low-hysteresis
4-54
DAQ-STC
© National Instruments Corporation