Rtsi Bus Interface Circuitry - National Instruments PCI E Series Programmer's Manual

RTSI Bus Interface Circuitry

© National Instruments Corporation
The counter counts the transitions, or edges, on the SOURCE line when the
GATE is enabled and generates timing signals at its OUT output pin. The
UPDOWN pin determines the direction of counting. Active polarities of
these pins are software selectable in the DAQ-STC. Notice that on the
PCI E Series boards only the SOURCE, GATE, and OUT pins are brought
out to the I/O connector. The UPDOWN pin for counter 0 is internally
connected to DIO6, and to DIO7 for counter 1. To drive the UPDOWN pin
from the connector, you must tri-state the corresponding DIO line.
The SOURCE of these counters can be selected to be one of the 10 PFI
lines, the seven RTSI lines, the internal 20 MHz or 100 kHz timebases, or
the TC of the other counter. With the last option, the two counters can be
concatenated. Similarly, the GATE can also be selected from a variety of
different sources. The sources for both of these signals are described in the
DAQ-STC Technical Reference Manual.
The PCI E Series is interfaced to the National Instruments RTSI bus. The
RTSI bus has seven trigger lines and a system clock line. You can wire all
National Instruments PCI E Series boards with RTSI bus connectors inside
the PCI bus computer and share these signals. Figure 2-19 shows a block
diagram of the RTSI bus interface circuitry.
2-25
Chapter 2 Theory of Operation
PCI E Series RLPM