Data Acquisition Timing Circuitry; Single-Read Timing - National Instruments PCI E Series Programmer's Manual

Chapter 2 Theory of Operation
board. This buffering also provides more time for the software or DMA to
respond and read the analog input data from the board. If the FIFO is full
and another conversion completes, an error condition called FIFO overflow
occurs and the data from that conversion is lost. The FIFO not empty,
half-full, and full flags are available to generate interrupts or DMA requests
for the data transfer.
Measurement reliability is assured through the onboard calibration
circuitry of the board. This circuitry uses an internal, stable 5 V reference
that is measured at the factory against a higher accuracy reference; its
value is then stored in the EEPROM. With this stored reference value,
the board can be recalibrated at any time under any number of different
environmental conditions in order to remove errors caused by time and
temperature drift. The EEPROM stores calibration constants that can be
read and then written to calibration DACs that adjust input offset, output
offset, and gain errors associated with the analog input section. When the
board leaves the factory, the upper one-fourth of the EEPROM is protected
and cannot be overwritten. The lower three-fourths is unprotected, and the
top fourth of that can be used to store alternate calibration constants for the
different conditions under which you use the board.

Data Acquisition Timing Circuitry

This section describes the different methods of acquiring A/D data from a
single channel or multiple channels.
From this section through the end of this manual, you are assumed to have
a working knowledge of the DAQ-STC features. These features are
explained in the DAQ-STC Technical Reference Manual. If you have not
read the functional description of each DAQ-STC module, you must do so
before completing this register-level programmer manual.

Single-Read Timing

To acquire data from the ADC, initiate a single conversion and read the
resulting value from the ADC FIFO buffer after the conversion is complete.
You can generate a single conversion in three different ways—apply an
active pulse to the CONVERT* pin of the I/O connector, generate a falling
edge on the sample-interval counter of the DAQ-STC, or strobe the
© National Instruments Corporation 2-11 PCI E Series RLPM