Figure 4-3. Dma Link Chaining Mode Structure - National Instruments PCI E Series Programmer's Manual

Register-level programmer manual, multifunction i/o boards for pci bus computers, register-level
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LKAR
© National Instruments Corporation
of transfer bytes for each buffer; MAR (Memory Address Register) stores
the buffer's physical address; DAR (Device Address Register) stores
default values for simple operation; LKAR (Link Address Register) stores
the physical address of the next node.
Before beginning the DMA transfers, LKAR must be loaded with the
physical address of the first node since the MITE needs to have an entry
point to access the link chain. After arming the DMA transfer, the MITE
goes through the link chain and loads the buffer's physical address into
MAR. Then the MITE transfers data from the FIFO to the buffers or from
the buffer to the output port. This process continues until the MITE reaches
the empty node, the node which contains all zeros.
Figure 4-3 illustrates the basic operation of the Link Chain Mode.
Use Physical Address
Use Physical Address
Use Physical Address

Figure 4-3. DMA Link Chaining Mode Structure

Link Chain
TCR
Use Physical Address
MAR
DAR
LKAR
TCR
MAR
Use Physical Address
DAR
LKAR
0 (Last Link)
0
0
0
4-59
Chapter 4
Programming
Buffer 0
Buffer 1
PCI E Series RLPM

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