Analog Input Circuitry; Figure 2-7. Analog Input And Data Acquisition Circuitry Block Diagram - National Instruments PCI E Series Programmer's Manual

Chapter 2 Theory of Operation
AISense
ACH0
ACH1
ACH2
ACH3
ACH4
ACH5
ACH6
ACH7
ACH8
ACH9
ACH10
...
...
...
...
ACH15*
Calibration
Sources
Channel
Number
*ACH63 for PCI-6071E, PCI-6031E, and PCI-6033E
PCI E Series RLPM
AIGND
Mode
Selection
Channel
Type

Figure 2-7. Analog Input and Data Acquisition Circuitry Block Diagram

Analog Input Circuitry

The general model for analog input on the PCI E Series boards
includes input multiplexer, multiplexer mode selection switches,
a software-programmable gain instrumentation amplifier, calibration
hardware, a sampling ADC, a 16-bit wide data FIFO, and a configuration
memory.
The configuration memory defines the parameters to use for each
conversion. Each entry in the configuration memory includes channel type,
channel number, bank, gain, polarity, dither, general trigger, and last
channel. The configuration memory is a 512-entry deep FIFO that is
initialized prior to the start of the acquisition sequence. It can be
incremented after every conversion, allowing the analog input
configuration to vary on a per conversion basis. Once the FIFO is empty,
Calibration
DACs
Dither
PGIA
Gain
Polarity
Convert
2-8
ADC FIFO
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