Pci Interface Circuitry - National Instruments PCI E Series Programmer's Manual

Chapter 2 Theory of Operation

PCI Interface Circuitry

PCI E Series RLPM
The PCI E Series interface circuitry consists of a PCI interface chip and
a digital control logic chip. The PCI interface chip provides a mechanism
for the PCI E Series to communicate with the PCI bus. The digital control
logic chip connects the PCI interface chip with the rest of the board. The
PCI E Series is fully compliant with PCI Local Bus Specification,
Revision 2.0. Therefore, the base memory address and the interrupt level
for the board are stored inside the PCI interface chip at power on. You do
not need to set any switches or jumpers. The PCI bus is capable of 8-bit,
16-bit, or 32-bit transfers, but PCI E Series boards use only 8-bit or
16-bit transfers.
The bus-mastering capabilities of the MITE provides high-speed data
transfer between the board and system memory. The MITE contains three
DMA channels that can be used simultaneously for data transfer with
analog input, analog output, and the general-purpose counters. The MITE
can control the PCI bus and transfer the data without interrupting the
host processor.
The DAQ-STC can generate interrupts from over 20 sources and can route
these interrupts to the INTA line on the PCI bus interface. Using two
interrupt lines, such as INTB, INTC or INTD, is not permitted for the
PCI E Series since each function in the PCI E Series does not have its own
configuration space. PCI E Series boards have the DAQ-STC IRQOUT0
line connected to the MITE interrupt input. Therefore, when setting up
interrupts you must route all interrupts through IRQOUT0. See the
DAQ-STC Technical Reference Manual for more information.
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