Daq-Stc Register Group; Fifo Strobe Register Group; Configuration Memory Clear Register; Adc Fifo Clear Register - National Instruments PCI E Series Programmer's Manual

Chapter 3 Register Map and Descriptions

DAQ-STC Register Group

The registers making up the DAQ-STC Register Group configure and control the DAQ-STC
system timing controller ASIC. These registers are described in the DAQ-STC Technical
Reference Manual.

FIFO Strobe Register Group

The three registers making up the FIFO Strobe Register Group are used to clear the three
FIFOs on the PCI E Series.

Configuration Memory Clear Register

Accessing the Configuration Memory Clear Register clears all information in the channel
configuration memory and resets the write pointer to the first location in the memory.
Window Address:
Type:
Word Size:
Bit Map:

ADC FIFO Clear Register

Accessing the ADC FIFO Clear Register clears all information in the ADC data FIFO.
Window Address:
Type:
Word Size:
Bit Map:

DAC FIFO Clear Register

Accessing the DAC FIFO Clear Register clears all information in the DAC data FIFO.
Note This Register is not valid for the PCI-6023E, PCI-6032E and PCI-6033E.
Window Address:
Type:
Word Size:
Bit Map:
PCI E Series RLPM
52 (hex)
Write-only
16-bit
Not applicable; no bits used
53 (hex)
Write-only
16-bit
Not applicable; no bits used
54 (hex)
Write-only
16-bit
Not applicable; no bits used
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