Clock Sources; Clock Control; Figure 11. Clock Tree Diagram - ST STM32303C-EVAL User Manual

UM1590
2.2

Clock sources

2.2.1

Clock control

The STM32F30x/31x internal clocks are derived from the HSE (clocked by the external
8 MHz crystal).
In this demonstration application, the various system clocks are configured as follows:
●
System clock is set to 72 MHz: the PLL is used as the system clock source: 72 MHz.
●
HCLK frequency is set to 72 MHz.
●
Timer clock (TIMCLK) is set to 72 MHz.
● PCLK1 is set to 36 MHz.
●
PCLK2 is set to 72 MHz.
Only the RTC is clocked by a 32 kHz external oscillator.
Figure 11

Figure 11. Clock tree diagram

illustrates the clock tree organization for this demo.
PLL multiplicator
x9
Doc ID 023892 Rev 1
SYSCLK
72MHz
AHB prescaler
/1
Running the demonstration
HCLK 72 MHz to AHB bus,
core, memory and DMA
72MHz
APB2 prescaler
/1
36MHz
APB1 prescaler
/2
RTC
MS31110V2
17/65