Bit Data Update Timing - Mitsubishi Electric MELSEC iQ-R AnyWireASLINK User Manual

Bit data update timing

Input
Unless the RJ51AW12AL receives the same data twice successively, data in the input area is not updated.
A minimum of one-transmission cycle time and a maximum of two-transmission cycle time are required as data response
time.
Therefore, when input data is shorter than two-transmission cycle time, the input data may not be captured depending on the
timing.
To ensure the response, provide an input signal that is longer than two-transmission cycle time.
■Case of minimum data response time
If no change is detected in input data between two sampling timings, communication in one-transmission cycle time is
possible.
(1)
(2)
(1) Sampling timing
(2) Change of the input data
(3) Update of the input data
■Case of maximum data response time
The input data is changed after a sampling, and thus the next sampling will be the first data reception. Time equivalent to two-
transmission cycle time is required.
(1)
(2)
(1) Sampling timing
(2) Change of the input data
(3) Update of the input data
Output
As the double verification of the bit data is executed on the slave module side, the time required is the same as that for input,
namely a minimum of one-transmission cycle time and a maximum of two-transmission cycle time.
APPX
118
Appendix 4 Processing Time
(1)
(3)
(1) (1)
(3)