Appendix 2
This section describes the I/O signals for the CPU module. The assignment of the I/O signals when the start I/O number of the
RJ51AW12AL is 0 is shown.
List of I/O signals
The following table lists I/O signals. Device X is an input signal from the RJ51AW12AL to the CPU module. Device Y is an
output signal from CPU module to the RJ51AW12AL.
Input signal
Device No.
X0
X1
X2
X3
X4
X5 to X7
X8
X9
XA
XB
XC
XD
XE
XF
X10
X11
X12
X13
X14
X15
X16
X17
X18 to X1F
*1 This signal is usable on the RJ51AW12AL of which first two digits of the production information are "03" or later.
I/O Signals
Signal name
Module READY
DP/DN short error
24V/DP short error
Transmission cable voltage drop error
DP/DN disconnection error
Use prohibited
AnyWireASLINK version compatibility inspection error
Backup/Restore unsupported error
Parameter access flag (with handshake)
Parameter accessing flag (with handshake)
Use prohibited
AnyWireASLINK version compatibility inspection executing flag
Use prohibited
Adjustment mode executing flag
Slave module alarm signal
Parameter access completion flag
Parameter access error
Use prohibited
Automatic address detection flag
Overlap address inspection flag
One slave module changing flag
Slave module replacement completion flag
Use prohibited
*1
*1
*1
*1
*1
*1
*1
*1
APPX
Appendix 2 I/O Signals
A
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