Table Of Contents - Xilinx Zynq-7000 Design Manual

Table of Contents

Revision History2
Table Of Contents4
Chapter 1: Introduction6
About This Guide6
Additional Support Resources6
Pcb Structures7
Chapter 2: Pcb Technology Basics7
Introduction7
Traces8
Planes8
Vias8
Pads And Antipads8
Lands9
Dimensions9
Transmission Lines10
Return Currents11
Pcb Decoupling Capacitors12
Recommended Pcb Capacitors Per Device12
Chapter 3: Power Distribution System12
Required Pcb Capacitor Quantities13
Required Pcb Capacitor Quantities Per Device (Pl)13
Required Pcb Capacitor Quantities Per Device (Ps)14
Capacitor Specifications15
Pcb Capacitor Specifications15
Pcb Bulk Capacitors16
Pcb Capacitor Placement And Mounting Techniques16
Pcb High-Frequency Capacitors16
Mid And High Frequency Capacitors16
Basic Pds Principles17
Noise Limits17
Example Capacitor Land And Mounting Geometries17
Role Of Inductance19
Simplified Pds Circuit19
Further Simplified Pds Circuit19
Capacitor Parasitic Inductance20
Parasitics Of A Real, Non-Ideal Capacitor21
Contribution Of Parasitics To Total Impedance Characteristics21
Pcb Current Path Inductance22
Capacitor Mounting Inductance22
Effective Frequency Example22
Example Cutaway View Of Pcb With Capacitor Mounting23
Plane Inductance24
Power-Ground Plane Sandwiches24
Ap Soc Mounting Inductance25
To Reduce Parasitic Inductance25
Pcb Stackup And Layer Order26
Capacitor Effective Frequency26
Capacitor Anti-Resonance28
Capacitor Placement Background29
Stabilization Capacitors30
Power Supply Consolidation30
Simulation Methods31
Eda Tools For Pds Design And Simulation31
Pds Measurements32
Noise Magnitude Measurement32
Noise Spectrum Measurements34
Infinite Persistence Measurement Of Same Supply34
Optimum Decoupling Network Design36
Troubleshooting37
Excessive Noise From Other Devices On The Pcb37
Parasitic Inductance Of Planes, Vias, Or Connecting Traces37
I/O Signals In Pcb Are Stronger Than Necessary38
I/O Signal Return Current Traveling In Sub-Optimal Paths38
Interface Types39
Single-Ended Versus Differential Interfaces39
Chapter 4: Selectio Signaling39
Sdr Versus Ddr Interfaces40
Single-Ended Signaling40
Modes And Attributes40
Input Thresholds41
Topographies And Termination41
Unidirectional Topographies And Termination42
Unidirectional Point-To-Point Topographies42
Parallel-Terminated Unidirectional, Point-To-Point Topography42
Series-Terminated Unidirectional, Point-To-Point Topography43
"Weak Driver" Unidirectional, Point-To-Point Topography43
Thevenin Parallel Termination44
Unidirectional Multi-Drop Topographies45
Basic Multi-Drop Topography46
Bidirectional Topography And Termination46
Bidirectional Point-To-Point Topographies47
Parallel Terminated Bidirectional Point-To-Point Topography47
"Weak Driver" Bidirectional Point-To-Point Topography48
Bidirectional Multi-Point Topographies50
Main Power Supplies51
Power Domains51
Chapter 5: Processing System (Ps) Power And Signaling51
Ps Ddr Power Supplies53
Filtering Circuit Layout53
Ps Ddr Interface I/O Supply53
Ps_Ddr_Vrn, Ps_Ddr_Vrp – Ps Ddr Termination Voltage54
Unused Ddr Memory54
Ps Mio Power Supplies54
Ps_Mio_Vref – Rgmii Reference Voltage55
Voltage Mode Configuration55
Power Sequencing55
Power Supply Ramp Requirements55
Ps Clock And Reset56
Ps_Clk – Processor Clock56
Ps_Por_B – Power On Reset56
Boot Mode Pin Mio[8]56
Dynamic Memory57
Ddr Interface Signal Pins57
Setting Mode Pins57
Ddr Unused Pins58
Dynamic Memory Implementation58
Ddr3/3L Board Implementation59
Ddr2 Board Implementation60
Ddr Supply Voltages61
Lpddr2 Board Implementation61
Ddr Voltage61
Ddr Termination62
Ddr Trace Length62
Ddr Max Trace Length62
Ddr Trace Impedance63
Ddr Delay Match63
Ddr Routing Topology63
Ddr Zq63
Mio/Emio Ip Layout Guidelines65
Can (Controller Area Network)65
Ethernet Gem65
Iic65
Temperature Sensing Diodes66
Trace Port Interface Unit (Tpiu)66
Uart66
Usb Ulpi66
Qspi67
Maximum Operating Frequency (Feedback Mode Enabled)67
Migration From Xc7Z030-Sbg485 To Xc7Z015-Clg485 Devices69
Functional And Performance Differences70
Package Differences70
Transceiver Differences70
Pcb Layout Considerations70
Software Considerations71
Xilinx Resources72
Product Support And Documentation72
Appendix A: Additional Resources And Legal Notices72
Zynq-7000 Ap Soc Documents73
Pl Documents – Device And Boards73
Solution Centers73
References73
Advanced Extensible Interface (Axi) Documents74
Software Documents74
Git Information74
Design Tool Documents74
Xilinx Ise Design Suite75
Xilinx Embedded Development Kit (Edk)75
Chipscope Pro Documentation75
Xilinx Problem Solvers75
Please Read: Important Legal Notices76